The transition from aluminum to copper required a change in process “architecture” (to damascene and dual-damascene) as well as a whole new set of process technologies. One process step used in producing copper damascene circuits is the formation of a “seed-” or “strike-” layer, which is then used as a base layer onto which copper is electroplated (“electrofill”). The seed layer carries the electrical plating current from the edge region of the wafer (where electrical contact is made) to the rest of the wafer surface, including trench and via structures located across the wafer surface. The seed film is typically a thin conductive copper layer. The seed film is typically separated from the insulating silicon dioxide or other dielectric by a diffusion barrier layer and/or an adhesion layer (e.g., a barrier/adhesion film of TaN/Ta/Ru below a copper seed). In some cases, the barrier/adhesion layer is composed of two or more films with varying properties to improve plateablity, to improve uniformity of the upper layers, or for other reason. The combination of processes of depositing barrier and seeding layers should yield a seed-layer structure that has good overall adhesion, excellent step coverage (more particularly, conformal and continuous amounts of metal deposited onto the side-walls of an embedded structure), and minimal closure or “necking” of the top of embedded features. Market trends of increasingly smaller features and alternative seeding processes drive the need for a capability to plate with a high degree of uniformity on increasingly thin seed layers. In the future, it is anticipated that the seed film might simply be composed of a relatively easily plateable barrier film, such as platinum, ruthenium, nickel, cobalt, or electroplating might be performed directly onto more classical barrier layer material such as tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, or laminates of these. Laminate composites of the metals, such as those just listed, are also under investigation. These materials typically have high specific resistivity (higher than metals typically used to carry electricity, such as copper, silver, aluminum, gold). Also, because they are thin, the mean-free-path of electrons therein is commensurate with the film thickness and the resistivity is greater than that predicted by typical scaling calculations (where resistance increases with length over cross sectional area). As a result, the resistance of a structure can be much greater than predicted by scaling calculations. Thus, thin resistive films pose extreme terminal effect difficulties. For example, when driving even a small 3 amp total current onto a 300 mm wafer uniformly through a 30 ohm per square ruthenium seed layer (a likely value for a 30-50 Å Ru film), the resultant within-seed center to edge voltage drop could be well over 2 volts (V).
To avoid introducing defects in the central device region and to plate effectively a large surface area, a plating tool typically makes numerous electrical contacts to the conductive seed layer only around the wafer periphery (all around the edge region of the wafer substrate). There is no direct contact made to the central region of the substrate. Hence, for highly resistive seed layers, the potential at the edge of the layer is significantly different than at the central region of the layer. In extreme cases, the scale of the potential differences within the metal film can be so great as to cause reaction at the wafer edge to occur at or near the electrochemical diffusion limit where a number of undesirable characteristics in the deposition can result (e.g., dendritic morphology), while simultaneously little or no reaction occurs at all at the inner regions of the wafer. Conventional means of decreasing plating non-uniformities (resulting from the significant center-to-edge variation of potential in the metal) utilize: (1) charge transfer inhibitors (e.g., plating suppressors and levelers, with the goal of creating a significant normal-to-the-surface voltage drop, thereby making the terminal voltage drop less or insignificant in comparison to the drop in the metal layer and electrolyte layers); or (2) very high ionic electrolyte resistances (yielding a similar effect). Unfortunately, typical organic additives cannot create surface polarization in excess of about 0.5 V. Thus, conventional uniformity-enhancing techniques cannot create polarization and related voltage drops required for very-thin-film seed plating, and hence cannot enable uniform electroplating of metal when the sheet resistances are large.
Furthermore, electrolyte composition is often determined by other plating factors, which can limit the range of usable or obtainable electrolyte resistivity. Electrolyte formulations having conductivities less than about 0.05 ohm−1 cm−1 require a near neutral pH value, no other supporting electrolytic components, and a relatively low metal concentration. The high-resistance electrolyte approach has limits and potentially several very significant problems: (1) the limited solubility of metal (e.g., copper) in higher pH baths without resorting to strong metal complexing (chelating) agents; (2) the (often associated) fact that a bath tends not to retain its film-morphology and feature-filling characteristics; (3) the added kinetic resistance associated with lower copper concentration is not favorable; and (4) a low mass-transfer-diffusion-limited plating rate.
The ability to electrofill features successfully, that is, the ability to electroplate very small, high aspect ratio features without voids or seams, is dependent on a number of parameters. Among these are: (1) plating chemistry; (2) feature shape, width, depth, and density; (3) local seed layer thickness; (4) local seed layer coverage; and (5) local plating current. These are substantially interrelated. For example, thinner seed layers can lead to greater potential differences between the center and edge of a wafer, and hence to large variations in current density during plating. Additionally, it is known that poor seed-layer side-wall coverage leads to higher average resistivities for current traveling normal to the feature direction (for trenches), also leading to large current-density differences between the center and edge of a wafer. It has generally been observed (substantially independent of plating chemistry) that effective electrofilling occurs only over a finite range of current densities or time-scales. While the appropriate electrofilling current density might depend on such things as feature shape, width or plating chemistry, for any given set of these parameters, there is a finite process window (i.e., localized current density) in which electrofilling can be successfully performed. Therefore, an apparatus and method of plating at a uniform current density over a whole wafer is needed.
Any change in conditions which increases seed layer resistivity or a seed layer's electrical path exacerbates the difficulty of achieving a uniform current distribution (required to maintain effectively uniformity of feature electrofilling across an entire wafer). A number of industry trends tend to increase seed layer resistivity. These include: (1) use of thinner seed layer films; (2) larger diameter wafers; (3) increasing pattern density; 4) smaller features and (5) increasing feature aspect ratios. Unfortunately, these trends produce more challenging conditions for electrofilling and are not generally amenable to maintaining uniform current density across a wafer. For example, for a given PVD (physical vapor deposition) seed deposition condition, smaller features are substantially more “necked” as compared to larger ones. As feature size shrinks, necking restricts the opening at the top opening of an etched feature. This effect causes the effective aspect ratio (i.e., the aspect ratio, AR, at which the plating process must begin plating into the feature) of the smaller width features to be substantially higher than that of the original, unseeded etched feature. To minimize this necking effect, a thinner seed layer with more conformal side wall coverage must be generally employed. However, a thinner seed layer can cause the voltage drop within the seed layer to be greater and the current distribution across the wafer to become more non-uniform, which (if left uncompensated) leads to poor electrofilling uniformity across the wafer.
It has been shown that the terminal resistance (wafer edge to center, ohms) (resistivity, differential resistance or resistance per unit length) from the edge to the center of the wafer is independent of radius. See E. K. Broadbent, E. J. McInerney, L. C. Gochberg, and R. L. Jackson, “Experimental and Analytical Study of Seed Layer Resistance for Copper Damascene Electroplating”, J. Vac. Sci. & Technol., B17, 2584 (1999). However, because the process of electrofilling requires that the current density scale as the wafer area, a 300 mm wafer requires 2¼ times more total current than a 200 mm wafer. With higher applied current at the edge (to maintain the same current density) and the same resistance, the potential drop from the edge to the center of the wafer is greater in a 300 mm wafer than in a 200 mm wafer.
FIG. 1 depicts schematically a cross-sectional view 100 of a conventional electroplating system 102 of the prior art. FIG. 1 contains an equivalent electrical circuit simplified to one dimension to explain the problem of “terminal effects” associated with plating (or removing) a thin metal film on a substrate surface. Conventional electroplating system 102 comprises conductive anode 104, which is electrically connected to a power supply 106. During electroplating, metal contained in electrolytic solution 108 is deposited on a thin conductive seed layer 110 located on a wafer substrate 112. The outer, peripheral edge 114 of seed layer 110 is connected to a negative terminal of power supply 106. The continuous resistance in seed layer 110 is simplified and represented by a discrete set of finite (in this case four) parallel circuit elements. The in-film resistor elements, Rf, represent the differential resistance from an outer radial point to a more central radial point on the wafer. The total current, It, supplied at edge 114 is distributed to the various surface elements, I1, I2, I3, I4, scaled by the total path resistances with respect to all the other resistances. The circuits more centrally located have a larger total resistance because of the cumulative/additive resistance of the Rf for those paths. Mathematically, the fractional current Fi through any one of the surface element paths is
                              F          i                =                                            I              i                                      I              t                                =                                                    Z                T                                            Z                i                                      =                                          1                                  (                                                            iR                      f                                        +                                          R                                              ct                        ,                        i                                                              +                                          Zw                      i                                        +                                          R                                              el                        ,                        i                                                                              )                                                                              ∑                  1                  n                                ⁢                                  1                                                            iR                      f                                        +                                          R                                              ct                        ,                        i                                                              +                                          Zw                      i                                        +                                          R                                              el                        ,                        i                                                                                                                                                    (        1        )            where n is the total number of parallel paths inot which the circuit is divided, i (sometimes used as a subscript) refers to the i-th parallel current path (from the edge terminal), t refers to the total circuit, I is current, Rf is the resistance in the metal film between each element (constructed, for simplicity, to be the same between each adjacent element), Rct is the local charge transfer resistance, Zw is the local diffusion (or Warberg) impedance and Rel is the electrolyte resistance. With this, Ii is the current through the i-th surface element pathway, and It is the total current to the wafer. The charge transfer resistance at each interfacial location is represented by a set of resistors Rct in parallel with the double layer capacitance Cdl, but for the steady state case does not effect the current distribution. The diffusion resistances, represented by the Warberg impedance (symbol Zw) and the electrolyte resistance (Rel) are shown in a set of parallel circuit paths, all in series with the particular surface element circuit. The several parallel current paths (e.g., the four paths I1-I4) depicted in FIG. 1 are available for carrying plating current to anode 104, the amount of current being influenced by the resistance and potential difference associated with each path. In practice, Rct and Zw are quite non-linear (depending on current, time, concentrations, and other factors), but this fact does not diminish the utility of this model. To achieve a substantially uniform current distribution, the fractional current should be the same, irrespective of the element position, i. When all terms other than the workpiece's seed layer's resistance terms, Rf (Rf1-Rf4 in FIG. 1) are relatively small, the fraction of current to the i-th element is
                    F        =                              1            i                                              ∑              1              n                        ⁢                          1              i                                                          (        2        )            Equation 2 has a strong i (location) dependence and is valid when no significant current-distribution compensating effects are active. In the other extreme, when Rct, Zw, Rel or the sum of these terms are greater than Rf, the fractional current approaches a uniform distribution. The limit of Equation 1 as these parameters become large relative to Rf is F=1/n, independent of location i.
FIG. 1 helps explain the physics behind several of the earlier approaches to solving the problem of plating non-uniformity. The goal was to achieve a uniform current distribution on a surface having a high sheet resistance. This meant trying to make the current that passes through each combination of series and parallel circuit paths (starting at the wafer periphery, exiting the wafer surface at various locations, and traversing the electrolyte to the counter electrode), be as equal as possible. To do this, the total path resistances needed to be as close to the same as possible. Some techniques of decreasing plating non-uniformity (i.e., enhancing plating uniformity) included utilizing: high Rct through the use of copper complexing agents or charge transfer inhibitors (e.g., plating suppressors and levelers) with the goal of creating a large normal-to-the-surface voltage drop, small Rf with respect to Rct; high ionic electrolyte resistances (yielding relatively large Rel); significant diffusion resistance (Zw); variations of plating current recipe to minimize voltage drop; and control of mass transfer rate to limit current density in areas of high interfacial voltage drop. See, for example, U.S. Pat. No. 6,074,544, issued Jun. 13, 2000, to Reid et al., and U.S. Pat. No. 6,162,344, issued Dec. 19, 2000, to Reid et al. These approaches have some limitations associated with the processes and with physical properties of the materials. Typical surface polarization derived by organic additives does not create polarization in excess of about 0.5 V (which is relatively small in comparison to the seed layer voltage drop that must be compensated). Also, because the conductivity of a plating bath is tied to its ionic concentration and pH, a decrease in bath conductivity directly and negatively impacts the rate of plating and the morphology of the plated material.
Other approaches have also been pursued to address the terminal effect problem. One class alters the effective ionic path resistance Rel for different current path elements (i.e., it provides a non-uniform Rel in the radial direction) to balance the film resistance with the resistance external to the film, as discussed in U.S. Pat. Nos. 6,126,798, 6,569,299 and 6,179,983, issued to Reid et al. This class includes patents teaching current shielding and concentric multiple anodes. See U.S. Pat. No. 6,773,571 issued Aug. 10, 2004, to Mayer et al., and U.S. Pat. No. 6,402,923, issued Jun. 11, 2002, to Mayer et al., both of which are incorporated herein by reference for all purposes. Another approach utilizes time-averaged exposure of substrate to plating current (e.g., with a rotating wafer and a current shield element) to plate the same thickness at all locations over time. See U.S. Pat. No. 6,027,631, issued Feb. 22, 2000, to Broadbent et al., and U.S. Pat. No. 6,919,010, issued Jul. 19, 2005, to Steven T. Mayer, titled “Uniform Electroplating Of Thin Metal Seeded Wafers Using Rotationally Asymmetric Variable Anode Correction”, which are incorporated herein by reference for all purposes. The use of asymmetrical shields has been used to change (tailor) plating uniformity. See U.S. Pat. No. 6,027,631, issued Feb. 22, 2000, to Broadbent, which is incorporated by reference. While the approaches discussed above are useful, they have potential limitations, such as: the difficulty of continuously (throughout the process) appropriately changing the resistance compensation when the thickness of the plated layer grows and thereby reduces the electronic resistance. See also U.S. patent application Ser. No. 10/739,822, filed Dec. 17, 2003, by Steven T. Mayer et al., titled, “Method For Planar Electroplating”, which is also incorporated herein by reference for all purposes.
Problems corresponding to those discussed above with respect to electroplating are also encountered in other electrolytic techniques, such as electropolishing, electroetching, electrochemical mechanical deposition (ECMD) and electrochemical mechanical polishing (ECMP). With anodic dissolution processes such as ECMP, as a metal film is removed and becomes thinner, the terminal resistance increases, potentially resulting in non-uniform current distribution and non-uniform removal of metal from the anodic substrate surface.
Thus, better methods and apparatuses for providing uniform electrochemical potential at a substrate surface are needed.